Linear Feedback Shift Register (LFSR) Calculator

Your details

Binary string of 0s and 1s, e.g. "1011". Length defines the register size. All-zeros locks an XOR LFSR.
Comma-separated bit positions that are XORed to produce the feedback bit. Position 1 is the MSB (leftmost bit). For a maximal-length 4-bit LFSR use taps 4, 3.
Number of clock cycles to simulate. Capped at 1000.
steps
Fibonacci: tapped bits are XORed externally and the result shifts into the MSB. Galois: feedback is applied internally at each tap position during the shift.
XOR is the standard choice and avoids the all-zeros lock-up. XNOR avoids the all-ones lock-up instead.
Output bit sequence
110101111000100

The stream of output bits produced over the requested clock steps

Detected period15 steps
Maximum possible period15 steps
Register size4bits
Ones in sequence8
Zeros in sequence7

4-bit Fibonacci LFSR with XOR feedback

  • Your tap selection produces a maximal-length sequence: period 15, which visits every non-zero state exactly once.
  • Of the 15 output bits, 8 are 1 (53.3%) and 7 are 0. A maximal LFSR produces almost equal 1s and 0s.
  • Fibonacci LFSRs are simpler to analyze: all tapped bits are XORed externally and the single feedback bit shifts into the MSB each cycle.

Next stepFor maximum-length sequences, use a primitive polynomial for your register size. See the reference table below for standard primitive polynomials up to 16 bits.

 = Powered by OnlyCalculators