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PCB Impedance Calculator

Enter your PCB trace geometry and dielectric properties to get the characteristic impedance (Z0) for microstrip, embedded microstrip, symmetric stripline, or asymmetric stripline traces. Switch to edge-coupled mode for differential pair impedance (Zdiff). Results update live and include propagation delay, capacitance, and inductance per millimetre. All dimensions default to mils; switch to millimetres with the unit selector.

Your details

Microstrip traces run on the outer copper layer over a dielectric. Stripline traces are buried between two ground planes. Edge-coupled types compute differential pair impedance.
All dimension inputs use this unit. Impedance is always in ohms.
Selecting a preset fills the dielectric constant field automatically.
Relative permittivity of the PCB substrate between the trace and the nearest ground plane. FR-4 is typically 4.3-4.7 at 1 GHz.
Width of the copper trace in the selected dimension unit.
mil
1 oz copper = 1.37 mil (34.8 µm). 0.5 oz = 0.7 mil. 2 oz = 2.74 mil. Enter in the selected unit.
mil
Height of the dielectric layer between the trace and the nearest reference plane. Also called substrate height or prepreg thickness.
mil
Optional: enter the trace length to compute total propagation delay, capacitance, and inductance for the full trace.
mil
Characteristic impedance (Z0)Controlled impedance
63.8ohm

Single-ended characteristic impedance of the trace

Differential impedance (Zdiff)-
Effective dielectric constant (Ereff)3.25
Propagation delay6.01ps/mm
Capacitance0.094pF/mm
Inductance0.384nH/mm
Total trace delay7.6ps
63.8 ohm
Low Z0<4050 ohm target40-60Moderate60-80High80-105Very high105+
065.55131.13915
Trace width (mil)

Z0 = 63.8 ohm

  • Characteristic impedance Z0 = 63.8 ohm. Most RF and high-speed digital traces target 50 ohm.
  • Signal propagation delay is 6.01 ps/mm. A 100 mm trace will delay your signal by about 601 ps.
  • Tolerance on controlled-impedance traces is typically +/-10% (standard) or +/-5% (precision). Coordinate with your PCB fab for layer stack-up details.

Next stepAdjust the trace width or dielectric height to shift Z0 toward your target. Wider traces lower impedance; thicker dielectrics raise it.

What is PCB trace impedance and why does it matter?

When a digital or RF signal travels along a PCB trace, the trace behaves as a transmission line with a characteristic impedance (Z0) determined by its geometry and the dielectric properties of the surrounding material. If the impedance of the trace does not match the source or load (or the cable or connector it is attached to), a portion of the signal is reflected back. At low frequencies these reflections are too fast to matter, but above about 50 MHz - roughly the point where the signal rise time becomes comparable to the round-trip delay of the trace - mismatches cause ringing, increased electromagnetic emissions, and unreliable logic levels. Controlled-impedance routing is therefore essential for high-speed digital interfaces such as USB, PCIe, HDMI, and LVDS, as well as for RF traces from antennas to amplifiers. PCB manufacturers offer stack-up engineering to hit a target impedance within a specified tolerance, typically 10% for standard controlled-impedance and 5% for precision work.

Microstrip vs. stripline: choosing the right trace type

A microstrip trace runs on the outer copper layer of the PCB, with the dielectric below and air above. Its impedance depends on trace width, copper thickness, and the dielectric height to the nearest ground plane. Because air has an effective Er of 1, the electromagnetic field partly travels through air and partly through the substrate, which is captured by the effective dielectric constant (Ereff) - a weighted average that is always less than the bulk Er of the laminate. Microstrip is cheaper to manufacture, easier to probe, and has lower propagation delay than stripline, but it radiates more and is more susceptible to noise. A stripline trace is buried between two ground planes, so the field is entirely inside the dielectric and Ereff equals the bulk Er. Stripline offers better shielding, lower EMI, and no coupling to adjacent layers, at the cost of higher propagation delay and increased manufacturing complexity. Embedded microstrip splits the difference: it is an outer-layer trace that has been covered with a thin layer of soldermask or dielectric, which raises the Ereff slightly above the open microstrip value.

How to use this calculator and interpret the results

Select the trace type that matches your PCB stack-up, choose your dimension unit (mil or mm), and pick the dielectric material. FR-4 is the most common laminate; Rogers 4003C and 4350B are used for RF work above about 1 GHz where FR-4's dielectric constant is too variable. Enter the trace width (W), copper thickness (T), and dielectric height (H). For differential pairs, also enter the edge-to-edge spacing (S) between the two traces; the calculator returns both the single-ended odd-mode impedance and the differential impedance Zdiff = 2 * Zodd. The impedance gauge shows your result relative to the 50 ohm single-ended target, and the chart shows how Z0 changes as you vary the trace width so you can tune your design. Wider traces always lower impedance; thicker dielectrics always raise it. Consult your PCB fab's controlled-impedance guidelines: they will specify the exact stack-up, tolerance, and any minimum line-and-space rules that apply to impedance-controlled layers.

Dielectric constant, propagation delay, and parasitic parameters

The dielectric constant (Er) of FR-4 typically ranges from 4.0 to 4.7 at 1 GHz and falls with increasing frequency, which is why high-frequency designs use low-loss materials such as Rogers 4003C (Er = 3.55, very stable) or Rogers 4350B (Er = 3.66). The effective dielectric constant (Ereff) calculated by this tool is the value that governs signal propagation: a higher Ereff means a slower propagation velocity and a longer electrical length for a given physical trace. Propagation delay (Tpd) is 3.336 * sqrt(Ereff) picoseconds per millimetre - for FR-4 microstrip, typically around 6-7 ps/mm. Capacitance and inductance per unit length follow from Z0 and Ereff: C = Tpd / Z0 in pF/mm and L = Tpd * Z0 / 1000 in nH/mm. These distributed parameters set the bandwidth and matching behaviour of the trace and are useful when designing matching networks or estimating crosstalk with adjacent lines.

Common PCB impedance targets by interface

InterfaceTopologyTarget impedanceTolerance
RF / antenna / SMASingle-ended50 ohm+/-10%
USB 2.0Differential pair90 ohm+/-15%
USB 3.0 / PCIeDifferential pair85 ohm+/-15%
HDMIDifferential pair100 ohm+/-15%
LVDSDifferential pair100 ohm+/-10%
Gigabit Ethernet (1000BASE-T)Differential pair100 ohm+/-15%
DDR3 / DDR4 data linesSingle-ended40-60 ohm+/-10%
DDR3 / DDR4 clockDifferential pair100 ohm+/-10%
RS-422 / RS-485Differential pair120 ohm+/-10%
CAN busDifferential pair120 ohm+/-10%

Target impedances for popular high-speed interfaces. Tolerance is typically +/-10% unless noted.

Frequently asked questions

What trace width gives 50 ohm impedance on standard FR-4?

For a standard 1.6 mm (63 mil) two-layer FR-4 board with 1 oz (1.37 mil) copper on the outer layer and a dielectric height of about 60 mil, a 50 ohm microstrip trace is roughly 100-110 mil (2.5-2.8 mm) wide. Thinner dielectric layers, commonly found in multi-layer boards with 6-8 mil prepreg, require a proportionally narrower trace - typically 10-15 mil for 50 ohm. Use this calculator with your fab's actual stack-up numbers for an accurate result.

What is the difference between single-ended and differential impedance?

Single-ended impedance (Z0) describes how a signal on one trace behaves relative to the ground plane. Differential impedance (Zdiff) describes how a signal propagating as a voltage difference between two coupled traces behaves. Zdiff = 2 * Zodd, where Zodd is the odd-mode impedance of each trace in the presence of the other. For tightly coupled pairs (small spacing), Zodd is lower than the single-ended Z0, so Zdiff is also lower. USB 2.0 targets 90 ohm differential; HDMI and LVDS target 100 ohm differential.

Why does my PCB fab use different numbers than this calculator?

This calculator uses the Hammerstad-Jensen closed-form equations for microstrip and the IPC-2141A empirical formulas for stripline. These are accurate to approximately 2-5%. PCB manufacturers typically use 2D field-solver software (such as Polar Si8000 or Speedstack) that accounts for trapezoid-shaped trace cross-sections, soldermask loading, and multi-layer interactions. Their results are more accurate but require the exact material data sheets and construction details. Use this tool for initial design and to understand sensitivities; then verify with your fab's controlled-impedance service.

How do I control impedance to +/-5% for RF designs?

Precision impedance control (better than +/-10%) requires using a low-Dk laminate with a tightly specified Er (Rogers materials are popular for this reason), ordering controlled-impedance fabrication with coupon testing, working with your fab to define exact trace width and dielectric height tolerances, and avoiding excessive soldermask coverage over RF traces. At microwave frequencies above about 5 GHz, you should also model the connector launch and via transitions because they dominate the impedance discontinuity.

Does copper weight affect impedance?

Yes, but less than trace width or dielectric height. Thicker copper (2 oz vs. 1 oz) slightly lowers Z0 because the effective width is wider after the thickness correction. For 1 oz (34.8 µm / 1.37 mil) copper on a 6 mil dielectric, the effect is about 1-2 ohm. Copper weight matters more for the minimum trace width your fab can reliably etch: heavier copper requires wider minimum traces to control under-etch.

What is propagation delay and how is it used?

Propagation delay (Tpd) is the time a signal takes to travel one unit length of trace. In FR-4 microstrip it is roughly 6.5-7 ps/mm; in stripline (same material) it is closer to 7-7.5 ps/mm because the full Er applies rather than an effective value below the bulk. Signal integrity engineers use Tpd to calculate the electrical length of a trace at a given frequency, to match lengths in length-matched differential pairs, and to budget for flight-time differences in source-synchronous interfaces such as DDR.

Sources

Written by Grace Mbeki, MSc Data Scientist & Educator · Nairobi, Kenya

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