MOSFET Threshold Voltage Calculator
Enter the key device parameters below to find the threshold voltage (Vth) of an n-channel or p-channel MOSFET. The calculator derives the Fermi potential, depletion charge, oxide capacitance, body-effect coefficient, and the final threshold voltage step by step. Adjust body-source voltage to see the body effect live. Results update instantly as you type.
What is the MOSFET threshold voltage?
The threshold voltage (Vth, also written VT or VGS(th)) is the minimum gate-to-source voltage needed to create a conducting channel between the drain and source of a MOSFET. Below Vth the channel does not form and the device is off (aside from small sub-threshold leakage current). Above Vth an inversion layer appears at the oxide-semiconductor interface and current flows. For an n-channel (NMOS) enhancement device Vth is positive; for a p-channel (PMOS) device it is negative. Vth is one of the most critical parameters in CMOS design because it controls both the switching speed and the standby leakage of every logic gate on a chip.
How Vth is derived from device physics
Threshold voltage is built up from three physical contributions. First, the flatband voltage (VFB) accounts for the work-function difference between the gate electrode and the semiconductor, plus any fixed charge trapped in the oxide. Second, the surface must be biased to twice the Fermi potential (2*phiF) to achieve strong inversion, where minority carriers outnumber majority carriers at the surface. The Fermi potential is phiF = (kT/q) x ln(NA/ni), where NA is the substrate doping, ni is the intrinsic carrier concentration, and kT/q is the thermal voltage (~25.85 mV at 300 K). Third, the charge that depletes the substrate below the gate must be supplied through the gate capacitance. This depletion charge per unit area is Qdep = sqrt(2 x epsSi x eps0 x q x NA x 2*phiF). Dividing by the oxide capacitance Cox = eps_ox x eps0 / tox gives the voltage needed to induce it. Summing the three contributions yields Vth0 = VFB + 2*phiF + Qdep/Cox.
The body effect: how source-body bias shifts Vth
When the source terminal is not at the same potential as the body (bulk), the depletion region under the gate widens, requiring more gate voltage to reach inversion. This is called the body effect (or substrate bias effect). The modified threshold voltage is Vth = Vth0 + gamma x (sqrt(2*phiF + VSB) - sqrt(2*phiF)), where gamma = sqrt(2 x epsSi x eps0 x q x NA) / Cox is the body-effect coefficient measured in V^0.5. Typical values of gamma range from 0.3 to 0.8 V^0.5. The body effect is exploited in stack-transistor circuits (series NMOS stacks in NAND logic) where the source of the top device sits above ground, raising its Vth and slightly worsening the pull-down speed. In analog design the body effect can create unwanted shifts in DC operating points. Some processes offer isolated n-wells so that the PMOS body is tied to the source, eliminating the body effect for those devices.
Temperature dependence and short-channel effects
Threshold voltage decreases with rising temperature at roughly -1.5 to -2.5 mV/K, because higher temperature reduces the bandgap and increases ni, which lowers the Fermi potential and therefore 2*phiF. This means hot devices are easier to turn on but harder to turn off, which raises standby leakage in digital circuits. Short-channel devices (gate length below about 100 nm) exhibit Drain-Induced Barrier Lowering (DIBL), where the electric field from the drain assists in forming the channel, effectively lowering Vth as drain voltage rises. At very short channel lengths, process variability causes Vth to fluctuate from device to device due to discrete dopant atoms in the tiny channel volume, a major challenge for SRAM bit cells. Modern FinFET structures largely mitigate DIBL and variability by surrounding the channel on multiple sides, giving the gate better electrostatic control.
Typical MOSFET Vth ranges by technology node
| Technology node | Process | Typical Vth (V) | Application |
|---|---|---|---|
| 180 nm | CMOS | 0.5 to 0.7 | Microcontrollers, mixed-signal |
| 90 nm | CMOS | 0.35 to 0.55 | Digital SoC, DSP |
| 45 nm | CMOS | 0.25 to 0.45 | High-performance CPU |
| 22 nm | FinFET | 0.2 to 0.35 | Mobile, server CPUs |
| 7 nm | FinFET | 0.15 to 0.25 | Leading-edge logic |
| HV / Power | DMOS | 1.0 to 4.0 | Motor drive, automotive |
| RF CMOS | 180 nm | 0.4 to 0.6 | LNA, mixers, PAs |
Representative threshold voltages for standard CMOS processes. Actual values depend on foundry and flavor (LVT/SVT/HVT).
Frequently asked questions
What is a typical threshold voltage for a modern MOSFET?
For standard CMOS logic at 180 nm, Vth is typically 0.5-0.7 V. At 22 nm FinFET nodes it drops to around 0.2-0.35 V. Most processes offer multiple flavors: high-Vth (HVT, lower leakage, slower), standard-Vth (SVT), and low-Vth (LVT, faster but higher leakage). Power MOSFETs for motor drive and switching regulators can have Vth in the 1-4 V range to avoid accidental turn-on.
Why does Vth decrease at higher temperatures?
Higher temperature increases the intrinsic carrier concentration (ni) and slightly reduces the silicon bandgap. Both effects lower the Fermi potential (phiF), which in turn reduces 2*phiF - the surface potential needed for strong inversion. The net result is a drop in Vth of roughly 1.5-2.5 mV per degree Kelvin. In a hot IC, transistors are easier to switch on but harder to fully turn off, raising leakage current.
How does oxide thickness affect threshold voltage?
Thinner oxide raises the oxide capacitance Cox, which reduces the voltage needed to induce the depletion charge (Qdep/Cox term) and also lowers the body-effect coefficient gamma. Both effects tend to reduce Vth. Halving tox roughly doubles Cox and cuts the Qdep/Cox term by half. Below about 3-4 nm, quantum-mechanical tunnelling through the SiO2 causes unacceptable gate leakage, which is why high-k dielectrics such as HfO2 replaced thin SiO2 in sub-45 nm nodes.
What is the body effect and when does it matter?
The body effect occurs when the source terminal is at a different potential from the body (bulk). It widens the depletion region, forcing the gate to supply more voltage to reach inversion. This raises Vth by gamma x (sqrt(2*phiF + VSB) - sqrt(2*phiF)). It matters most in stacked transistors (series-connected NMOS in NAND gates, current mirrors, cascode amplifiers) and in dynamic circuits where nodes float. Tying the body to the source eliminates the effect but is only possible in SOI or triple-well processes.
What is flatband voltage and how is it set?
Flatband voltage (VFB) is the gate voltage at which the semiconductor bands are flat (no band bending, no charge in the silicon). It depends on the work-function difference between the gate material and the substrate, plus any fixed charge at the oxide-semiconductor interface or within the oxide. For an n+ poly-silicon gate on a p-type substrate, VFB is typically around -0.5 to -1.0 V. Changing the gate material (e.g. using a metal gate in high-k/metal-gate processes) or adding ion-implanted dopants directly below the gate (threshold-adjust implant) shifts VFB and therefore Vth.
What is the difference between enhancement mode and depletion mode?
An enhancement-mode MOSFET requires a gate voltage exceeding Vth to turn on, so it is off at VGS = 0. It is the dominant type in digital CMOS. A depletion-mode device has a conducting channel at VGS = 0 (Vth is negative for NMOS) and needs a negative gate voltage to turn off. Depletion-mode MOSFETs appear in some analog and RF circuits, and in high-electron-mobility transistors (HEMTs) used in power amplifiers.